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1

Hybrid Wordlength Optimization Methods of Pipelined FFT Processors

Cheng-Yeh Wang, Chin-Bin Kuo, Jing-Yang Jou

Journal:

IEEE Transactions on Computers

Year:

2007

Language:

english

File:

PDF, 5.77 MB

english, 2007

2

An automorphic approach to verification pattern generation for SoC design verification using port-order fault model

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2002

Language:

english

File:

PDF, 348 KB

english, 2002

3

Converter-free multiple-voltage scaling techniques for low-power CMOS digital design

Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2001

Language:

english

File:

PDF, 242 KB

english, 2001

4

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - An efficient approach for hierarchical submodule extraction

Yi-Wei Lin,, Jing-Yang Jou,

Year:

2004

Language:

english

File:

PDF, 280 KB

english, 2004

5

A divide-and-conquer-based algorithm for automatic simulation vector generation

Chia-Chih Yen,, Jing-Yang Jou,, Kuang-Chien Chen,

Journal:

IEEE Design & Test of Computers

Year:

2004

Language:

english

File:

PDF, 337 KB

english, 2004

6

[IEEE 2011 IEEE International Test Conference (ITC) - Anaheim, CA, USA (2011.09.20-2011.09.22)] 2011 IEEE International Test Conference - Design-for-debug layout adjustment for FIB probing and circuit editing

Chen, Kuo-An, Chang, Tsung-Wei, Wu, Meng-Chen, Chao, Mango C.-T., Jou, Jing-Yang, Chen, Sonair

Year:

2011

Language:

english

File:

PDF, 283 KB

english, 2011

7

A design-for-verification technique for functional pattern reduction

Chien-Nan Jimmy Liu,, I-Ling Chen,, Jing-Yang Jou,

Journal:

IEEE Design & Test of Computers

Year:

2003

Language:

english

File:

PDF, 319 KB

english, 2003

8

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - An AVPG for SOC design verification with port order fault model

Chun-Yao Wang,, Shing-Wu Tung,, Jing-Yang Jou,

Year:

2001

Language:

english

File:

PDF, 448 KB

english, 2001

9

An automatic controller extractor for HDL descriptions at the RTL

Chien-Nan Jimmy Liu,, Jing-Yang Jou,

Journal:

IEEE Design & Test of Computers

Year:

2000

Language:

english

File:

PDF, 86 KB

english, 2000

10

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - A novel approach for functional coverage measurement in HDL

Chien-Nan Jimmy Liu,, Chen-Yi Chang,, Jing-Yang Jou,, Ming-Chih Lai,, Hsing-Ming Juan,

Year:

2000

Language:

english

File:

PDF, 461 KB

english, 2000

11

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Estimating Likelihood of Correctness for Error Candidates to Assist Debugging Faulty HDL Designs

Tai-Ying Jiang,, Chien-Nan Jimmy Liu,, Jing-Yang Jou,

Year:

2005

Language:

english

File:

PDF, 607 KB

english, 2005

12

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - RLC effects on worst-case switching pattern for on-chip buses

Shang-Wei Tu,, Jing-Yang Jou,, Yao-Wen Chang,

Year:

2004

Language:

english

File:

PDF, 255 KB

english, 2004

13

[IEEE ISCAS 2003. International Symposium on Circuits and Systems - Bangkok, Thailand (25-28 May 2003)] Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. - SoC design integration by using automatic interconnection rectification

Chun-Yao Wang,, Shing-Wu Tung,, Jing-Yang Jou,

Year:

2003

Language:

english

File:

PDF, 439 KB

english, 2003

14

[IEEE ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems - Sydney, NSW, Australia (6-9 May 2001)] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) - Grouped input power sensitive transition an input sequence compaction technique for power estimation

Heng-Liang Huang,, Yeong-Ren Chen,, Jing-Yang Jou,, Wen-Zen Shen,

Year:

2001

Language:

english

File:

PDF, 446 KB

english, 2001

15

[IEEE 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC) - Sydney, Australia (2012.01.30-2012.02.2)] 17th Asia and South Pacific Design Automation Conference - Thread affinity mapping for irregular data access on shared Cache GPGPU

Hsien-Kai Kuo,, Kuan-Ting Chen,, Lai, Bo-Cheng Charles, Jing-Yang Jou,

Year:

2012

Language:

english

File:

PDF, 185 KB

english, 2012

16

Simultaneous floor plan and buffer-block optimization

Jiang, I.H.-R., Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2004

Language:

english

File:

PDF, 480 KB

english, 2004

17

An efficient heterogeneous tree multiplexer synthesis technique

Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2005

Language:

english

File:

PDF, 225 KB

english, 2005

18

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2006

Language:

english

File:

PDF, 359 KB

english, 2006

19

Observability Analysis on HDL Descriptions for Effective Functional Validation

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2007

Language:

english

File:

PDF, 631 KB

english, 2007

20

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

Tai-Ying Jiang, Liu, C.-N.J., Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2009

Language:

english

File:

PDF, 655 KB

english, 2009

21

An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging

Chia-Chih Yen, Jing-Yang Jou

Journal:

IEEE Transactions on Computers

Year:

2006

Language:

english

File:

PDF, 3.15 MB

english, 2006

22

Automatic interconnection rectification for SoC design verification based on the port order fault model

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2003

Language:

english

File:

PDF, 744 KB

english, 2003

23

Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR

Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1997

Language:

english

File:

PDF, 221 KB

english, 1997

24

On computing the minimum feedback vertex set of a directed graph by contraction operations

Hen-Ming Lin, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2000

Language:

english

File:

PDF, 294 KB

english, 2000

25

Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing

Jiang, I.H.-R., Yao-Wen Chang, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2000

Language:

english

File:

PDF, 351 KB

english, 2000

26

On automatic-verification pattern generation for SoC with port-order fault model

Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2002

Language:

english

File:

PDF, 487 KB

english, 2002

27

Verification of Pin-Accurate Port Connections

Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang

Journal:

IEEE Design & Test of Computers

Year:

2008

Language:

english

File:

PDF, 662 KB

english, 2008

28

Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures

Jing-Yang Jou, Abraham, J.A.

Journal:

Proceedings of the IEEE

Year:

1986

Language:

english

File:

PDF, 889 KB

english, 1986

29

On circuit clustering for area/delay tradeoff under capacity and pin constraints

Juinn-Dar Huang,, Jing-Yang Jou,, Wen-Zen Shen,, Hsien-Ho Chuang,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

1998

Language:

english

File:

PDF, 257 KB

english, 1998

30

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM

Che-Hua Shih,, Juinn-Dar Huang,, Jing-Yang Jou,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2009

Language:

english

File:

PDF, 384 KB

english, 2009

31

[ACM Press the 2003 conference - Kitakyushu, Japan (2003.01.21-2003.01.24)] Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC - Simultaneous floorplanning and buffer block planning

Jiang, Iris Hui-Ru, Chang, Yao-Wen, Jou, Jing-Yang, Chao, Kai-Yuan

Year:

2003

Language:

english

File:

PDF, 112 KB

english, 2003

32

[IEEE 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) - Huntington Beach, CA, USA (2012.11.9-2012.11.10)] 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) - A formal method to improve SystemVerilog functional coverage

Cheng, An-Che, Yen, Chia-Chih, Jou, Jing-Yang

Year:

2012

Language:

english

File:

PDF, 1.74 MB

english, 2012

33

A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs

Lai, Bo-Cheng Charles, Kuo, Hsien-Kai, Jou, Jing-Yang

Journal:

IEEE Transactions on Computers

Year:

2015

Language:

english

File:

PDF, 848 KB

english, 2015

34

[IEEE 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) - Yokohama (2013.1.22-2013.1.25)] 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) - Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

Hsien-Kai Kuo,, Ta-Kan Yen,, Lai, Bo-Cheng Charles, Jing-Yang Jou,

Year:

2013

Language:

english

File:

PDF, 152 KB

english, 2013

35

[IEEE 2006 IEEE International SOC Conference - Austin, TX (2006.09.24-2006.09.27)] 2006 IEEE International SOC Conference - Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Huang, Chun-ming, Lee, Kuen-jong, Yang, Chih-chyau, Hu, Wen-hsiang, Wang, Shi-shen, Chen, Jeng-bin, Chen, Chi-shi, Van, Lan-da, Wu, Chien-ming, Tsai, Wei-chang, Jou, Jing-yang

Year:

2006

Language:

english

File:

PDF, 460 KB

english, 2006

36

[IEEE Comput. Soc. Press Fifth Asian Test Symposium (ATS'96) - Hsinchu, Taiwan (20-22 Nov. 1996)] Proceedings of the Fifth Asian Test Symposium (ATS'96) - Easily testable data path allocation using input/output registers

Li-Ren Huang,, Jing-Yang Jou,, Sy-Yen Kuo,, Wen-Bin Liao,

Year:

1996

Language:

english

File:

PDF, 649 KB

english, 1996

37

[IEEE 2011 International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2011.03.14-2011.03.16)] 2011 12th International Symposium on Quality Electronic Design - Mixed non-rectangular block packing for non-Manhattan layout architectures

Wu, Meng-Chen, Chen, Hung-Ming, Jou, Jing-Yang

Year:

2011

Language:

english

File:

PDF, 362 KB

english, 2011

38

[IEEE Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Napa Valley, CA, USA (Nov. 30-Dec. 2, 2005)] Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Che-Hua Shih,, Juinn-Dar Huang,, Jing-Yang Jou,

Year:

2005

Language:

english

File:

PDF, 257 KB

english, 2005

39

[IEEE Tenth Asian Test Symposium - Kyoto, Japan (19-21 Nov. 2001)] Proceedings 10th Asian Test Symposium - An improved AVPG algorithm for SoC design verification using port order fault model

Chun-Yao Wang,, Shing-Wu Tung,, Jing-Yang Jou,

Year:

2001

Language:

english

File:

PDF, 562 KB

english, 2001

40

[IEEE Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) - San Jose, CA, USA (1997.11.13-1997.11.13)] Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 - A power modeling and characterization method for macrocells using structure information

Jiing-Yuan Lin,, Wen-Zen Shen,, Jing-Yang Jou,

Year:

1997

Language:

english

File:

PDF, 548 KB

english, 1997

41

[IEEE Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) - Sonoma Valley, CA, USA (2004.11.10-2004.11.12)] Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) - Enhancing sequential depth computation with a branch-and-bound algorithm

Chia-Chih Yen,, Jing-Yang Jou,

Year:

2004

Language:

english

File:

PDF, 519 KB

english, 2004

42

[IEEE Comput. Soc. Press Fifth Asian Test Symposium (ATS'96) - Hsinchu, Taiwan (20-22 Nov. 1996)] Proceedings of the Fifth Asian Test Symposium (ATS'96) - An efficient PRPG strategy by utilizing essential faults

Li-Ren Huang,, Jing-Yang Jou,, Sy-Yen Kuo,

Year:

1996

Language:

english

File:

PDF, 677 KB

english, 1996

43

[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

Kuang-Chin Cheng,, Jing-Yang Jou,

Year:

2008

Language:

english

File:

PDF, 162 KB

english, 2008

44

[IEEE 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) - Hsinchu, Taiwan (27-29 April 2005)] 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). - On-chip bus encoding for LC cross-talk reduction

Jim-Sheng Huang,, Shang-Wei Tu,, Jing-Yang Jou,

Year:

2005

Language:

english

File:

PDF, 808 KB

english, 2005

45

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Hierarchical floorplan design on the Internet

Jiann-Horng Lin,, Jing-Yang Jou,, Hui-Ru Jiang,

Year:

1999

Language:

english

File:

PDF, 435 KB

english, 1999

46

[IEEE International Symposium on VLSI Technology Systems and Applications - Taipei, Taiwan (8-10 June 1999)] 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) - An efficient algorithm for the multiple constant multiplication problem

Chen, M., Jing-Yang Jou,, Hen-Ming Lin,

Year:

1999

Language:

english

File:

PDF, 342 KB

english, 1999

47

[IEEE Comput. Soc. Press Fourth Asian Test Symposium - Bangalore, India (23-24 Nov. 1995)] Proceedings of the Fourth Asian Test Symposium - An effective BIST design for PLA

Year:

1995

Language:

english

File:

PDF, 469 KB

english, 1995

48

[IEEE Conference of Asia and South Pacific Design Automation 2003 - Kitakyushu, Japan (21-24 Jan. 2003)] Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. - Simultaneous floorplanning and buffer block planning

Hui-Ru Jiang, I., Yao-Wen Chang,, Jing-Yang Jou,, Kai-Yuan Chao,

Year:

2003

Language:

english

File:

PDF, 421 KB

english, 2003

49

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - An efficient logic extraction algorithm using partitioning and circuit encoding

Huang, L., Tai-Ying Jiang,, Jing-Yang Jou,, Heng-Liang Huang,

Year:

2004

Language:

english

File:

PDF, 285 KB

english, 2004

50

[IEEE ASP-DAC '97: Asia and South Pacific Design Automation Conference - Chiba, Japan (28-31 Jan. 1997)] Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference - A power driven two-level logic optimizer

Jyh-Mou Tseng,, Jing-Yang Jou,

Year:

1997

Language:

english

File:

PDF, 426 KB

english, 1997